A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning

摘要

Field programmable gate arrays (FPGAs) provide designers with the ability toquickly create hardware circuits. Increases in FPGA configurable logic capacityand decreasing FPGA costs have enabled designers to more readily incorporateFPGAs in their designs. FPGA vendors have begun providing configurable softprocessor cores that can be synthesized onto their FPGA products. While FPGAswith soft processor cores provide designers with increased flexibility, suchprocessors typically have degraded performance and energy consumption comparedto hard-core processors. Previously, we proposed warp processing, a techniquecapable of optimizing a software application by dynamically and transparentlyre-implementing critical software kernels as custom circuits in on-chipconfigurable logic. In this paper, we study the potential of a MicroBlazesoft-core based warp processing system to eliminate the performance and energyoverhead of a soft-core processor compared to a hard-core processor. Wedemonstrate that the soft-core based warp processor achieves average speedupsof 5.8 and energy reductions of 57% compared to the soft core alone. Our datashows that a soft-core based warp processor yields performance and energyconsumption competitive with existing hard-core processors, thus expanding theusefulness of soft processor cores on FPGAs to a broader range of applications.